1. Field of the Invention
The present invention generally relates to an image processor, and more particularly, to an encoder and a decoder for HD Photo.
2. Description of the Background Art
Microsoft Corporation proposes HD Photo (or JPEG XR) as a still image file format that offers higher image quality than JPEG while requiring more simple circuit configuration and computation than JPEG 2000.
An encoder for HD Photo includes a frequency transform unit performing predetermined frequency transform (PCT), and a pre-filter performing predetermined prefiltering so as to reduce block artifacts. The frequency transform unit performs frequency transform with a pixel block having 4 pixels in column×4 pixels in row as a unit region for processing. The pre-filter performs prefiltering with a region which overlaps with plural unit regions for processing by the frequency transform unit as a unit region for processing, before frequency transform is performed. The frequency transform unit performs frequency transform on a first pixel block that includes plural unit regions for processing as a target block, and the pre-filter performs prefiltering on a second pixel block that is 2 pixels each larger horizontally and vertically than the first pixel block as a target block. The size of the first pixel block is 16 pixels in column×16 pixels in row in the first stage, and is 4 pixels in column×4 pixels in row in the second stage. The size of the second pixel block is 20 pixels in column×20 pixels in row in the first stage, and is 8 pixels in column×8 pixels in row in the second stage.
In this Specification, to facilitate the description, only an example of processing an image in YUV444 format is described. As to chrominance signals when processing an image in YUV422 format, the size of the first pixel block is 16 pixels in column×8 pixels in row in the first stage, and is 4 pixels in column×2 pixels in row in the second stage. The size of the second pixel block is 20 pixels in column×12 pixels in row in the first stage, and is 8 pixels in column×6 pixels in row in the second stage. Similarly, as to chrominance signals when processing an image in YUV420 format, the size of the first pixel block is 8 pixels in column×8 pixels in row in the first stage, and is 2 pixels in column×2 pixels in row in the second stage. The size of the second pixel block is 12 pixels in column×12 pixels in row in the first stage, and is 6 pixels in column×6 pixels in row in the second stage.
A decoder for HD Photo includes a frequency inverse transform unit performing frequency inverse transform that corresponds to the above frequency transform, and a post-filter performing postfiltering that corresponds to the above prefiltering. The frequency inverse transform unit performs frequency inverse transform with a pixel block having 4 pixels in column×4 pixels in row as a unit region for processing. The post-filter performs postfiltering with a region which overlaps with plural unit regions for processing by the frequency inverse transform unit as a unit region for processing, after frequency inverse transform is performed. The frequency inverse transform unit performs frequency inverse transform on a first pixel block that includes plural unit regions for processing as a target block, and the post-filter performs postfiltering on a second pixel block that is shifted from the first pixel block by 2 pixels each horizontally and vertically as a target block. The sizes of the first and second pixel blocks are 16 pixels in column×16 pixels in row in the first stage, and are 4 pixels in column×4 pixels in row in the second stage.
The details of HD Photo are disclosed in, for example, “HD Photo—Photographic Still Image File Format”, [online], 7 Nov. 2006, Microsoft Corporation, [searched in the Internet on 10 Oct. 2007], <URL: http://www.microsoft.com/whdc/xps/hdphotodpk.mspx>. The details of JPEG XR are disclosed in, for example, “Coding of Still Pictures—JBIG JPEG”, [online], 19 Dec. 2007, ISO/IEC JTC 1/SC 29/WG1 N 4392, [searched in the Internet on 4 Mar. 2008], <URL: http://www.itscj.ipsj.or.jp/sc29/open/29view/29n9026t.doc>
FIG. 17 illustrates prefiltering in HD Photo. A pixel block PB101 is a target pixel block of frequency transform having 16 pixels in column×16 pixels in row. A pixel block PB102 is a target pixel block of prefiltering having 20 pixels in column×20 pixels in row. The pixel block PB102 is 2 pixels each larger to the left, right, top and bottom than the pixel block PB101.
Prefiltering of a region R101 indicated by a sanded pattern has already been performed in processing each of the pixel blocks above to the left of and just above the pixel block PB101, and the pixel signals after prefiltering have been transmitted to the frequency transform unit. Prefiltering of a region R102 indicated by vertical stripes has already been performed in processing the pixel block above to the left of the pixel block PB101, and the pixel signals after prefiltering have been stored in a first memory (not shown). The first memory is a line memory with capacity in accordance with the length of a row in a pixel plane. Prefiltering of a region R103 indicated by zigzag lines has already been performed in processing the pixel block just above the pixel block PB101, and the pixel signals after prefiltering have been stored in the first memory. Prefiltering of a region R104 indicated by a sanded pattern has already been performed in processing the pixel block on the left of the pixel block PB101, and the pixel signals after prefiltering have been transmitted to the frequency transform unit. Prefiltering of a region R105 indicated by a netted pattern has already been performed in processing the pixel block on the left of the pixel block PB101, and the pixel signals after prefiltering have been stored in a second memory (not shown). Unlike the above line memory, capacity of the second memory is independent of the length of a row in a pixel plane. Prefiltering of a region R106 indicated by a lattice pattern has already been performed in processing the pixel block on the left of the pixel block PB101, and the pixel signals after prefiltering have been stored in the first memory.
In this state, the pixel signals of a pixel block PB103 having 16 pixels in column×16 pixels in row indicated by thick, broken lines are inputted to the pre-filter. The pre-filter performs prefiltering on these pixel signals inputted thereto. The pixel signals after prefiltering of the pixel block PB101 are transmitted to the frequency transform unit. The pixel signals after prefiltering of a region R107 indicated by lateral stripes are stored in the second memory. The pixel signals after prefiltering of a region R108 indicated by oblique lines are stored in the first memory.
Since the pixel signals after prefiltering of the region R108 are to be used in processing each of the pixel blocks just under and below to the right of the pixel block PB101, the pixel signals after prefiltering of the region R108 need to remain stored in the first memory until processing of these pixel blocks is completed. The same is true of other pixel blocks in the same tier as the pixel block PB101. Consequently, capacity of the first memory increases in proportion to the length of a row in a pixel plane. Thus processing a large size image requires increased capacity of the first memory, resulting in increase in overall circuit size of the image processor.
FIG. 18 illustrates postfiltering in HD Photo. A pixel block PB201 is a target pixel block of frequency inverse transform having 16 pixels in column×16 pixels in row. A pixel block PB202 is a target pixel block of postfiltering having 16 pixels in column×16 pixels in row. The pixel block PB202 is shifted from the pixel block PB201 by 2 pixels each to the left and top. Postfiltering of the region in the pixel block PB201 which does not overlap with the pixel block PB202 is performed in processing each of the pixel blocks on the right of, just under, and below to the right of the pixel block PB201.
The pixel signals of a region R201 indicated by zigzag lines have already been transmitted from the frequency inverse transform unit to the post-filter in processing each of the pixel blocks above to the left of and just above the pixel block PB201, and the pixel signals before postfiltering have been stored in a third memory (not shown). The third memory is a line memory with capacity in accordance with the length of a row in a pixel plane. The pixel signals of a region R202 indicated by a netted pattern have already been transmitted from the frequency inverse transform unit to the post-filter in processing the pixel block on the left of the pixel block PB201, and the pixel signals before postfiltering have been stored in a fourth memory (not shown). Unlike the above line memory, capacity of the fourth memory is independent of the length of a row in a pixel plane. The pixel signals of a region R203 indicated by a sanded pattern have already been transmitted from the frequency inverse transform unit to the post-filter in processing the pixel block on the left of the pixel block PB201, and the pixel signals before postfiltering have been stored in the third memory.
In this state, the pixel signals of the pixel block PB201 are inputted from the frequency inverse transform unit to the post-filter. The post-filter performs postfiltering on the pixel signals of the pixel block PB202. The pixel signals before postfiltering of a region R204 indicated by lateral stripes are stored in the fourth memory. The pixel signals before postfiltering of a region R205 indicated by oblique lines are stored in the third memory.
Since the pixel signals before postfiltering of the region R205 are to be used in processing each of the pixel blocks just under and below to the right of the pixel block PB201, the pixel signals before postfiltering of the region R205 need to remain stored in the third memory until processing of these pixel blocks is completed. The same is true of other pixel blocks in the same tier as the pixel block PB201. Consequently, capacity of the third memory increases in proportion to the length of a row in a pixel plane. Thus processing a large size image requires increased capacity of the third memory, resulting in increase in overall circuit size of the image processor.